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512K x 8 Static RAM
MSM8512C - 020 Issue 5.2 April 2001
Description
The MSM8512C is a 512K x 8 SRAM monolithic device available in Chip Size BGA (Ball Grid Array) package, with access times of 20ns. The device is available to commercial and industrial temperature grades. The Chip Size BGA provides an ultra high density memory packaging solution. The Chip Size BGA occupies less than 50% of the board area of conventional SOP, SOJ and TSOP II packages.
Block Diagram
/CS /OE /WE
A0 A1 A2 A3 A4 A5 A6 A7 A8
512K x 8 SRAM
D0 D1 D2 D3 D4 D5 D6 D7
Features
* Access times of 20 ns. * 5V + 10%, (3.3V Under Development) * Commercial & Industrial temperature grades * Chip Size BGA. * 48 pad, 1mm pad pitch, package. * Eutectic 63/67 solder ball attach. * Low Power Dissipation. Operating 1 W (max) Standby (CMOS) 66mW (max) * Completely Static Operation. * 4 layer BT substrate with power and ground planes. * Pinout and footprint will remain the same in the event of a die shrink.
Pin Definition See page 2.
Pin Functions
Description Address Input Data Input/Output Chip Select Write Enable Output Enable No Connect Power Ground Signal A0~A18 D0~D7 /CS /WE /OE NC VCC GND
A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
Package Details
48D - 48 Ball, 1mm pitch Chip Size BGA Max. Dimensions (mm) - 8.00 x 10.00 x 1.40
Pin Definition - MSM8512B
Pinout (Top View)
1
Pin A1 Ident.
2
3
4
5
6
A B C D E F G H
A4 NC D0 VCC VSS D3
A2 /CS NC D1 D2 NC
A0 A1 A3 A18 NC A5 A7 A8
A17 A15 NC A16 NC /OE NC NC A9 D6 D5 NC D7 VSS VCC D4
A13 NC
NC /WE NC A6
A11 A14 NC A10 A12 NC
Note : Pinout shows top view, balls facing down.
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Issue 5.2 April 2001
Absolute Maximum Ratings(1)
DC Operating Conditions
Parameter Voltage on any pin relative to VSS Power Dissipation Storage Temperature
Symbol VT PT TSTG
Min -0.5 to 1 -55 to
Max +6.0
Unit V W
+150
O
C
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability
Recommended Operating Conditions
Parameter Supply Voltage Input High Voltage Input Low Voltage Operating Temperature Symbol VCC VIH VIL TA TAI Min 4.5 2.2 -0.3 0 -40 Typ 5.0 Max 5.5 6.0 0.8 70 85 Unit V V V
O O
C C (I Suffix)
DC Electrical Characteristics (VCC=5V+10%, TA= -40OC to 85OC)
Parameter Input Leakage Current Output Leakage Current Symbol ILI ILO Test Condition
VIN=VSS to VCC /CS=VIH or /OE=VIH or /WE=VIL, VOUT=VSS to VCC Min. Cycle, 100% Duty /CS=VIL, VIN=VIH or VIL, IOUT=0mA Min. Cycle, /CS=VIH f=0MHz, CS>VCC-0.2V, VIN>VCC-0.2V or VIN<0.2V IOL=8.0mA IOH=-4.0mA
Min -2 -2
Typ -
Max 2 2
Unit A A
Operating Supply Current Standby Supply Current
ICC1 ISB ISB1
2.4
-
180 60 12 0.4 -
mA mA mA V V
Output Voltage
VOL VOH
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Issue 5.2 April 2001
Capacitance (VCC = 5.0V+10% TA = 0OC to 70OC)
Parameter Input Capacitance I/O Capacitance Symbol CIN CI/O Test Condition VIN=0V VI/O=0V Typ max 10 10 Unit pF pF
Test Conditions
* * * * * Input pulse levels : 0V to 3.0V Input rise and fall times : 3ns Input and Output timing reference levels : 1.5V Output Load : See Load Diagram. VCC = 5V+10%
Output Load
I/O Pin
166 1.76V 30pF
Functional Description
/CS H L L L /WE X H H L /OE X H L X Mode Not Select Output Disable Read Write I/O Pin High-Z High-Z DOUT DIN Supply Current ISB,ISB1 ICC ICC ICC
Note : X = Don't Care
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Issue 5.2 April 2001
Read Cycle
20 Parameter Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output Chip Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Symbol Min Max Units tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH 20 3 0 0 0 3 20 20 9 9 9 ns ns ns ns ns ns ns ns ns
AC Operating Conditions
Write Cycle
20 Parameter Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write Write Pulse Width (/OE High) Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z Symbol tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW Min Max 20 14 0 14 14 0 0 10 0 3 9 Units ns ns ns ns ns ns ns ns ns ns
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Issue 5.2 April 2001
Read Cycle 1
(Address Controlled, /CS=/OE=VIL, /WE=VIH)
tRC Address tOH Data Out Previous Data Valid tAA Data Valid
Timing Waveforms
Read Cycle 2
(/WE = VIH)
tRC Address tAA tCO /CS tOHZ tOE /OE tOLZ tLZ(4,5) Data Out Valid Data tOH tHZ(3,4,5)
NOTES(READ CYCLE) 1. /WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device. 5. Transition is measured 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with /CS=VIL. 7. Address valid prior to coincident with /CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
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Issue 5.2 April 2001
Write Cycle 1
(/OE = Clock)
tWC Address tAW /OE tCW(3) /CS tWR(5)
tAS(4) /WE
tWP(2)
tDW High Z Data In tOHZ(6) High Z(8) Data Out Valid Data
tDH
NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ; A write ends at the earliest transition /CS going high or /WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 6. If /OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10.When /CS is low I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
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Issue 5.2 April 2001
Write Cycle 2
(/OE = Low Fixed)
tWC Address tAW tCW(3) /CS tAS(4) /WE tDW High Z Data In tWHZ(6) High Z(8) Data Out Valid Data tOW (10) (9) tDH tWP(2) tWR(5)
NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ; A write ends at the earliest transition /CS going high or /WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 6. If /OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10.When /CS is low I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
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Issue 5.2 April 2001
Write Cycle 3
(/CS = Controlled)
tWC Address tAW tCW(3) /CS tAS(4) /WE tDW High Z Data In tLZ High Z Data Out tWHZ(6) High Z(8) Valid Data tDH High Z tWP(2) tWR(5)
NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ; A write ends at the earliest transition /CS going high or /WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 6. If /OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10.When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
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Issue 5.2 April 2001
Package Details
Chip Size BGA - 48 pad
10.00 Max.
8.00 Max.
Top View
Pin A1 Ident. 1.00+0.07
1.40 Max.
CL
A1
1.00+0.07
CL
Bottom View
H6
General Reliability Data High Temperature Operating Life High Temperature Storage Life Autoclave Temperature Cycling Moisture Sensitivity
O
125 C / 6V / 1000hrs 150 C / 1000hrs 121 C / 100% RH / 168hrs -55 ~ 125 C / 1000 cycles JEDEC Level 3 30 C / 60% RH / 192hrs 30 ~ 45 C/Watt
O O O O O
O
JA Thermal Performance
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Issue 5.2 April 2001
Ordering Information
Ordering Information
MSM8512CB I - 020/48D
48D Speed 48D = 48 Pad package, 1mm Pitch 020 = 20ns
Temp. Range/Screening Blank = Commercial I = Industrial Power Consumption Package Die Revision Memory Organisation Family Technology Blank = Standard Power B = Chip Size BGA C = `C' Rev die. 8512 = 512K x 8 M = Monolithic S = SRAM
Note : Although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for a particular purpose. Our products are subject to a constant process of development. Data may be changed without notice. Products are not authorised for use as critical components in life support devices without the express written approval of a company director.
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Issue 5.2 April 2001

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